Kirti Gupta,Neeta Pandey,Maneesha Gupta: search on Z-Library

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1

Low-power tri-state buffer in MOS current mode logic

Kirti Gupta,Neeta Pandey,Maneesha Gupta

Journal:

Analog Integrated Circuits and Signal Processing

Year:

2013

Language:

english

File:

PDF, 281 KB

english, 2013

2

[IEEE 2011 International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT) - Aligarh, India (2011.12.17-2011.12.19)] 2011 International Conference on Multimedia, Signal Processing and Communication Technologies - A novel active shunt-peaked MOS Current Mode Logic C-element for asynchronous pipelines

Gupta, Kirti, Pandey, Neeta, Gupta, Maneesha

Year:

2011

Language:

english

File:

PDF, 863 KB

english, 2011

3

[IEEE 2011 Annual IEEE India Conference (INDICON) - Hyderabad, India (2011.12.16-2011.12.18)] 2011 Annual IEEE India Conference - A new improved current mode logic style with feedback for wireless communication

Sridhar, Ranjana, Gupta, Kirti, Pandey, Neeta, Gupta, Maneesha

Year:

2011

Language:

english

File:

PDF, 306 KB

english, 2011

4

Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells

Gupta, Kirti, Pandey, Neeta, Gupta, Maneesha

Journal:

Microelectronics Journal

Year:

2013

Language:

english

File:

PDF, 433 KB

english, 2013

5

[IEEE 2013 International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT) - Aligarh, India (2013.11.23-2013.11.25)] IMPACT-2013 - A novel high speed MCML square root carry select adder for mixed-signal applications

Gupta, Kirti, Radhika,, Pandey, Neeta, Gupta, Maneesha

Year:

2013

Language:

english

File:

PDF, 870 KB

english, 2013

6

[IEEE 2014 International Conference on Signal Processing and Integrated Networks (SPIN) - Noida, Delhi-NCR, India (2014.02.20-2014.02.21)] 2014 International Conference on Signal Processing and Integrated Networks (SPIN) - Low power D-latch design using MCML tri-state buffers

Radhika,, Pandey, Neeta, Gupta, Kirti, Gupta, Maneesha

Year:

2014

Language:

english

File:

PDF, 226 KB

english, 2014

7

[IEEE 2012 IEEE 5th India International Conference on Power Electronics (IICPE) - Delhi, India (2012.12.6-2012.12.8)] 2012 IEEE 5th India International Conference on Power Electronics (IICPE) - Low power Multi-Threshold MOS Current Mode Logic asynchronous pipeline circuits

Gupta, Kirti, Pandey, Neeta, Gupta, Maneesha

Year:

2012

Language:

english

File:

PDF, 906 KB

english, 2012

8

[IEEE 2011 2nd International Conference on Computer and Communication Technology (ICCCT) - Allahabad, India (2011.09.15-2011.09.17)] 2011 2nd International Conference on Computer and Communication Technology (ICCCT-2011) - Performance comparison of MCML and PFSCL gates in 0.18 μm CMOS technology

Gupta, Kirti, Sridhar, Ranjana, Chaudhary, Jaya, Pandey, Neeta, Gupta, Maneesha

Year:

2011

Language:

english

File:

PDF, 191 KB

english, 2011

9

[IEEE 2011 International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT) - Aligarh, India (2011.12.17-2011.12.19)] 2011 International Conference on Multimedia, Signal Processing and Communication Technologies - A new current mode logic style with feedback for digital applications

Gupta, Kirti, Sridhar, Ranjana, Chaudhary, Jaya, Pandey, Neeta, Gupta, Maneesha

Year:

2011

Language:

english

File:

PDF, 723 KB

english, 2011

10

[IEEE 2013 International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT) - Aligarh, India (2013.11.23-2013.11.25)] IMPACT-2013 - Performance improvement of PFSCL gates through capacitive coupling

Gupta, Kirti, Pandey, Neeta, Gupta, Maneesha

Year:

2013

Language:

english

File:

PDF, 1.47 MB

english, 2013

11

New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic

Gupta, Kirti, Sridhar, Ranjana, Chaudhary, Jaya, Pandey, Neeta, Gupta, Maneesha

Journal:

Journal of Electrical and Computer Engineering

Year:

2011

Language:

english

File:

PDF, 405 KB

english, 2011

12

MCML D-Latch Using Triple-Tail Cells: Analysis and Design

Gupta, Kirti, Pandey, Neeta, Gupta, Maneesha

Journal:

Active and Passive Electronic Components

Year:

2013

Language:

english

File:

PDF, 574 KB

english, 2013

13

Dynamic Positive-Feedback Source-Coupled Logic (D-PFSCL)

Gupta, Kirti, Pandey, Neeta, Gupta, Maneesha

Journal:

International Journal of Electronics

Year:

2016

Language:

english

File:

PDF, 1.63 MB

english, 2016

14

MOS Current Mode Logic with Capacitive Coupling

Gupta, Kirti, Pandey, Neeta, Gupta, Maneesha

Journal:

ISRN Electronics

Year:

2012

Language:

english

File:

PDF, 1.67 MB

english, 2012

15

Model and Design of Improved Current Mode Logic Gates (Differential and Single-ended) ||

Gupta, Kirti, Pandey, Neeta, Gupta, Maneesha

Year:

2020

Language:

english

File:

PDF, 5.48 MB

english, 2020